1. Field of the Invention
The present invention relates generally to phase measurement circuitry and in particular to phase detection circuitry capable of accommodating signal inputs of widely varying amplitudes while maintaining relatively low power consumption.
2. Description of Related Art
Phase detection circuitry has a wide range of applications. FIG. 1 shows two input sinusoidal signals IN1 and IN2 of the same frequency but differing in phase. The two signals IN1 and IN2 can be respectively expressed as A1*sin(ω0t+φ1) and A2*sin(ω0t+φ2), respectively. Assuming that IN2 is leading IN1, the phase difference Δφ is defined as being equal to φ2−φ1. FIG. 2 is a prior art circuit of a standard multiplier 15 sometimes referred to as a Gilbert multiplier. If the two signals IN1 and IN2 are relatively large in magnitude as compared to the thermal voltages VT of the transistors of the FIG. 2 Gilbert multiplier, the input signals operate to completely turn ON or turn OFF the transistors. In that event, the multiplier 15 operates as a phase detector, with the differential output signal Out switching between +(IEE*RC) and −(IEE*RC) depending upon the phase relationship between the inputs.
The above is illustrated by reference to the timing diagram of FIG. 3. When the two input signals IN1 and IN2 have relatively large magnitudes as compared to VT, the signals can be approximately represented as digital signals as shown in FIG. 3. Multiplier 15 can be considered to operate in a manner similar to an exclusive NOR circuit. If the inputs IN1 and IN2 differ, then signal Out is low, otherwise the output is high. As can be seen, signal IN2 leads signal IN1 in phase by a phase difference of Δφ as also shown in FIG. 1. During the period corresponding to Δφ when IN1 is low and IN2 is high, all of the IEE current is flowing through one of the resistors RC to produce a minimum value of signal Out having an associated area A1. As also indicated, when both signals IN1 and IN2 are high during the remaining portion of the half cycle π, signal Out is at a maximum value and has an associated area A2.
Inspection of the FIG. 3 plot indicates that the average value of signal Out for the range 0≦Δφ≦π is as follows:Vavg=(A2−A1)/π
Taking into consideration of the actual voltages produced at the output of the multiplier, for this same range of 0≦Δφ≦π, the average voltage can also be expressed as follows:
                                                                                          Vavg                  =                                    ⁢                                                                                    V                        MULT                                            ⁡                                              [                                                                                                            (                                                              π                                -                                                                  Δ                                  ⁢                                                                                                                                          ⁢                                  φ                                                                                            )                                                        /                            π                                                    -                                                      (                                                          Δ                              ⁢                                                                                                                          ⁢                                                              φ                                /                                π                                                                                      )                                                                          ]                                                              ⁢                                                                                  ⁢                    or                                                                                                                        =                                    ⁢                                                            V                      MULT                                        ⁡                                          [                                              1                        -                                                                              (                                                          2                              ⁢                              Δ                              ⁢                                                                                                                          ⁢                              φ                                                        )                                                    /                          π                                                                    ]                                                                                                    ⁢                                          ⁢          with          ⁢                                          ⁢          the          ⁢                                          ⁢          symbol          ⁢                                          ⁢                                    V              MULT                        ⁡                          [              …              ]                                ⁢                                          ⁢          indicating          ⁢                                          ⁢          that          ⁢                                          ⁢          the          ⁢                                          ⁢          average                ⁢                                  ⁢                  value          ⁢                                          ⁢          is          ⁢                                          ⁢          a          ⁢                                          ⁢          function          ⁢                                          ⁢          of          ⁢                                          ⁢          the          ⁢                                          ⁢          terms          ⁢                                          ⁢          within          ⁢                                          ⁢          the          ⁢                                          ⁢                      brackets            .                                              (        1        )            
The average value of signal Out for the range −π≦Δφ≦0 is as follows:Vavg=(A2−A1)/π=VMULT[(π+Δφ)/π+(Δφ/π)]orVavg=VMULT[1+(2Δφ)/π]  (2)
A low pass filter is used to obtain Vavg, the average multiplier output signal, with Vavg being a direct measure of the phase difference Δφ between IN1 and IN2.
FIG. 4 illustrates an ideal phase detector output signal 22 after low pass filtering. The reference point is for signal IN1 having a phase φ1 of 0° with the phase φ2 of signal IN2 varying from −175° to +175°. The detector output signal is at a maximum value 22A of 621.6 mV when φ2 is in phase with φ1 and drops down in a linear fashion to about −0.59 at 22B for −175° and at 22C for +175°.
FIG. 5 depicts a conventional phase detector for detecting a phase difference between sinusoidal inputs IN1 and IN2. Two amplification channels A and B are provided, with each channel having N number of separate differential gain stages. The gain stages function to ensure that the input voltages to the multiplier M1 are sufficiently large. The detector output is theoretically independent of any variations in the magnitudes of inputs IN1 and IN2. A low pass filter F1 is provided to provide the average multiplier output and to remove the ripple at 2× the input frequency. The typical prior art phase detector further includes amplitude mismatch circuitry 24 for measuring the magnitude ratio or gain between the two input signals IN1 and IN2 which has an application generally unrelated to carrying out the phase detection function.
Ideally, the two amplifier channels A and B introduce a small and but equal delay into each channel so that no phase errors are introduced. In order to minimize amplitude dispersion and a resulting phase error, the amplifier stages of each channel must have a very high bandwidth. In order to obtain a phase accuracy of around 1° to 2°, a gain stage bandwidth of 16× to 32× of the maximum input frequency is needed. However, such wide bandwidth requires a lot of power, a big drawback in mobile and other low power applications.
There is a need for an accurate phase detector which can be used in low power applications. As will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings, the various disclosed embodiments are capable of providing this capability.